Device for adjusting circuits before encapsulation

ABSTRACT

A device for adjusting an integrated circuit before encapsulation includes a first MOS transistor having a gate and a source connected together, and a body connected to a voltage reference. A first resistor is connected in parallel with the first MOS transistor. A second MOS transistor is connected in series with the first MOS transistor. The second MOS transistor has a gate and a source connected together, and a body connected to the voltage reference. A second resistor is connected in parallel with the second MOS transistor. A first terminal is connected to the source of the first MOS transistor, and a second terminal is connected to the source of the second MOS transistor. The first terminal is accessible externally after the integrated circuit has been encapsulated.

This application is a national phase of PCT International ApplicationNo. PCT/FR02/00503 filed on Feb. 11, 2002 under 35 U.S.C. § 371.

FIELD OF THE INVENTION

The present invention relates to analog and digital integrated circuits.These circuits desirably use the smallest possible silicon area toreduce costs while still maintaining high precision.

BACKGROUND OF THE INVENTION

A silicon wafer that has undergone various steps of etching and/ordeposition of conductive, semiconductor or insulation layers is putthrough a sorting step intended to remove defective circuits. Thesorting step is followed by a packaging or encapsulation step.

During the sorting step, each circuit on a wafer is tested to check itsconformance,to specifications. A circuit can be considered satisfactory,rejected, or alternatively, a candidate for adjustment. Adjustment isperformed by imposing given electrical voltages and/or currents onterminals of the integrated circuit. Some of these terminals may nolonger be accessible once the circuit is encapsulated.

SUMMARY OF THE INVENTION

In view of the foregoing background, an object of the present inventionis to provide a device for adjusting an integrated circuit during thesorting step, prior to its encapsulation.

This and other objects, advantages and features in accordance with thepresent invention are provided by a device forming part of an integratedcircuit, and is disposed between an external contact terminal accessibleeven after encapsulation and the remainder of the circuit that isintended to perform a specific function.

The integrated electronic circuit may comprise a plurality of MOStransistors. The circuit comprises at least a first and a second MOStransistor arranged in series. Each transistor comprises a gate and asource short-circuited together, and a base connected to ground of theintegrated circuit. The circuit may advantageously comprise a firstresistance connected in parallel with the first transistor, and a secondresistance connected in parallel with the second transistor.

The circuit may further comprise a third transistor connected in serieswith the first and second transistors. This transistor comprises a gateand a source short-circuited together, and a body connected to ground ofthe integrated circuit. The circuit may also further comprise a thirdresistance connected in parallel with the third transistor. This is theglobal ground of the circuit, which is necessary for its satisfactoryoperation.

In one embodiment of the invention, the circuit may comprise aconnection terminal that is connected to the source of the firsttransistor and is accessible after the circuit is encapsulated.Alternatively, a resistance can be connected between the terminal andthe source of the first transistor.

In another embodiment of the invention, the circuit may comprise aconnection terminal that is connected to the source of the secondtransistor and is not accessible after the circuit is encapsulated, anda connection terminal that is connected to the drain of the secondtransistor and is not accessible after the circuit is encapsulated.

In yet another embodiment of the invention, the circuit may furthercomprise a connection terminal that is connected to the drain of thethird transistor and is not accessible after the circuit isencapsulated. More generally, the connection terminal connected to thedrain of the nth transistor can be connected to the rest of the circuit.The term “series-arranged MOS transistor” is understood to meantransistors in which the source of the n+1th transistor is connected tothe drain of the nth transistor.

The MOS transistors may be isolated or non-isolated transistors. Thebody connector is preferably adjacent the drain.

Another aspect of the present invention is directed to a method ofadjusting an electrical resistance in an integrated electronic circuitcomprising a plurality of series-connected MOS transistors, eachprovided with a parallel-connected resistance. The bodies of the MOStransistors may be connected to one another. A first voltage is appliedto a MOS transistor at its body, its gate and its source and a secondvoltage is applied to its drain in order to break down the MOStransistor.

The bodies of the MOS transistors are preferably connected to a globalground of the circuit, and the bodies of the MOS transistors areshort-circuited to the gate and to the source of the MOS transistor thatis to be broken down.

The first voltage is preferably constant and the second voltage is amonotonic ramp. The first voltage can be zero and the second voltage canbe increasing. The breakdown of the MOS transistor can be effected byavalanche of the drain/substrate junction, irreversible breakdown of thedrain/substrate junction and a short-circuit between the drain and thesource. The difference between the first and second voltages is about 16V. The breakdown current can be less than 100 mA.

The invention applies to both n-MOS and p-MOS transistors.

The use of “snapback” MOS transistors makes it possible to achieve ashort-circuit and thus a resistance inside an integrated circuit byacting on the pins or terminals of the integrated circuit that can beaccessed prior to encapsulation. A component formed in this manner takesup little space on a silicon wafer and is therefore inexpensive. Thefact that the gate and the source of the MOS transistor areshort-circuited ensures permanent blocking of the MOS transistor andkeeps it from affecting operation of the rest of the electronic circuit.After breakdown, the MOS transistor can be considered the equivalent ofan open circuit.

The invention makes use of a natural characteristic of MOS transistors,that of having parasitic components, particularly a bipolar transistor.In some configurations, such parasitic components are harmful. Duringelectrostatic discharge, circuits can be seriously damaged by turn-on ofthe parasitic transistor.

Conversely, the invention utilizes the parasitic bipolar transistor ofthe MOS transistor to make it a short circuit and obtain a resistancehaving a predetermined value between the drain and the source of the MOStransistor, i.e., between the collector and the emitter of the parasiticbipolar transistor. This component can be considered an antifuse. A fuseis a closed circuit in the normal state and an open circuit afterbreakdown. Here, the MOS transistor is an open circuit before breakdownand a closed circuit after breakdown, with a low residual resistancevalue.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be better understood from a study of thedetailed description of a few embodiments, taken strictly asnon-limiting examples and illustrated by the appended drawings, wherein:

FIG. 1 is a characteristic operating curve of a MOS transistor accordingto the prior art;

FIG. 2 is a cross-sectional view of a MOS transistor according to thepresent invention;

FIG. 3 is a diagram of the device according to the present invention;and

FIG. 4 is a cross-sectional view of a variation of a MOS transistoraccording to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

As can be seen in FIG. 1, where the drain voltage is plotted on theabscissa (horizontal axis) and the drain current is plotted on theordinate (vertical axis), an n-MOS transistor has four operatingregions. Region 1 is the conventional linear operation of a MOStransistor. Region 2 is a saturation-mode operation, in which currentvaries only very slightly with voltage. Region 3 is known as theavalanche region, with a weakening of the drain/substrate junctioncaused by avalanche of the junction. Finally, Region 4 is the turn-on ofthe parasitic bipolar transistor, with the curve showing a firstbreakdown, referenced 5, which is reversible, and a second breakdown,referenced 6, which is destructive and therefore irreversible.

Beyond the second breakdown 6, the current varies extremely rapidly withvoltage, with the slope of the curve being almost vertical. Since thebreakdown process, also known as a second breakdown is irreversible, itis possible to move along the curve beginning at the second breakdown! 6by moving up, which translates into a decrease in the resistance offeredby the MOS transistor broken down in this way, insofar as the currentcan be seen to increase against a substantially constant drain voltage.

FIG. 2 shows the structure of the various components of the MOStransistors. The MOS transistor comprises a drain 8, a source 9 and agate 10 formed on a body 11, also known as the bulk. A parasitic bipolartransistor 12 forms in the body 11. Its collector is formed by the drain8 and its emitter by the source 9, and its base can be modeled asconnected to ground by a substrate resistance 13 and by a current source14 connected to the drain 8.

In the arrangement according to the invention, the drain 8 is connectedto a first supply voltage, while the source 9, gate 10 and body 11 areshort-circuited and are connected to a second supply voltage. When theMOS transistor reaches saturation, a high voltage on the drain triggersavalanche of the drain/body junction by generating electron-hole pairs,thus creating a body current. The voltage at the terminals of the bodyresistance increases, thereby biasing the source/body junction. Theparasitic bipolar transistor thus undergoes flashover and the phenomenonof breakdown occurs.

At high currents the component goes into the irreversible secondbreakdown state, represented by destruction of the polysilicon crystallattice of the channel formed between the drain and the source. Afteravalanche of the collector/body junction of the parasitic bipolartransistor, the emitter connected to ground serves to forward-bias thebody/emitter junction, which causes the snapback effect. To trigger theavalanche phenomenon, a sufficient voltage must be imposed on the drainto reverse-bias the drain/body junction. This voltage depends on thedoping characteristics and is proportional to the square of theelectrical field.

The current generator 14 shown in FIG. 2 between the collector and thebody of the parasitic bipolar transistor simulates the leakage currentsof the drain/body junction in an initial phase. Thereafter, it serves tosimulate avalanche of the junction and biasing of the parasitic bipolarnpn-type transistor.

By way of example, tests were performed using HF4 CMOS technology withan n-MOS transistor having the following channel dimensions: width (W)=1μm and length (L)=0.7 μm. The source was grounded, and a voltage rampranging from 8 to 18 V with current limitation was applied to the drain.With a current of 2 mA, a post-breakdown resistance of 300 ohms wascreated. With a current of 10 mA, a post-breakdown resistance of 60 ohmswas obtained, and with a current of 100 mA, a post-breakdown resistanceof 11 ohms was obtained. It will be noted that with a drain voltage ofless than 11 V, the drain/base junction is not in avalanche, andtherefore no current passes through the drain/source channel. Beyondthis voltage the phenomenon sets in, with the creation of a conductivepath allowing the passage of current. Once the breakdown voltage isreached, all the available current flows into the channel and aresistance is created.

It is particularly advantageous to use transistors whose channel is asshort as possible, since the shorter the channel, the lower thebreakdown voltage, due to the increase in the drain current and theincrease in the number of electron-hole pairs generated. The channelwidth is constant. A decrease in the channel width brings about adecrease in the voltage and the current of the second breakdown 6illustrated in FIG. 1. Even if the width of the channel has no effect onthe voltage of the first breakdown 5, a reduced width will increase theheating effect of the second breakdown 6, since the lines of force willbe more unidirectional, implying a decrease in the torque of the secondbreakdown. It is therefore particularly advantageous to use small-sizedMOS transistors.

When a MOS transistor is used in the snapback mode, the substrate isconnected to the lowest potential of the circuit to reverse-bias all theparasitic diodes existing between drain 8 and source 9, on the one hand,and body 11 on the other. Source 9 and base 11 are short-circuited. Gate10 is also short-circuited to source 9 and to the body 11 to deactivatethe transistor.

Resistances arranged in parallel can be adjusted with this type ofsnapback MOS transistor. Reference is directed to French Patent No.2,795,557 for more information.

FIG. 3 shows an embodiment of the invention comprising threeseries-arranged resistances to be adjusted, referenced 15, 16 and 17.Resistance 15 is connected to a ground terminal 18 that will beconnected to one of the external pins or terminals of the circuit at thetime of encapsulation, and resistance 17 is connected to the rest of thecircuit (not shown). The device further comprises three MOS transistors19, 20, 21. Each transistor is provided with a gate, respectively 22, 23and 24, a drain, respectively 25, 26 and 27, a source, respectively 28,29 and 30, and a body, respectively 31, 32 and 33.

Transistor 19 is connected in parallel with resistance 15, transistor 20in parallel with resistance 16 and transistor 21 in parallel withresistance 17. The gate and the source of each transistor 19, 20 and 21are short-circuited. Bodies 31 to 33 of transistors 19 to 21 are allconnected to terminal 18. Gate 22 and source 28 of transistor 19 areconnected to terminal 18. Drain 25 of transistor 19 and gate 23 andsource 29 of transistor 20 are connected to the common point betweenresistances 15 and 16 and to an adjustment terminal 34 that can be nolonger accessible after the circuit is encapsulated. Drain 26 oftransistor 20 and gate 24 and source 30 of transistor 21 are connectedto the common point between resistances 16 and 17 and to an adjustmentterminal 35 that can be no longer accessible after the circuit isencapsulated. Drain 27 of transistor 21 is connected to the otherterminal of resistance 17, to the rest of the circuit (not shown) and toan adjustment terminal 36 that can be no longer accessible after thecircuit is encapsulated

To break down transistor 21, terminals 18 and 35 are together connectedto ground and a positive voltage ramp is applied to terminal 36. Ifterminal 18 were left unconnected, the snapback phenomenon would notoccur due to the impossibility of avalanching the drain/body junctionand thus of forward-biasing the body/transmitter junction.

If transistor 20 is to be broken down, terminals 18 and 34 are connectedtogether and a positive voltage ramp is applied to bump 35. To breakdown transistor 19, a positive voltage is applied to terminal 34 andterminal 18 is connected to ground.

A system of low-value series-connected resistances can thus be adjustedby MOS transistors in a reproducible and reliable manner. A non-isolatedMOS transistor takes up much less area than an isolated MOS transistor,for example an area of 7 μm out of 14 μm instead of 40 μm out of 40 μm,thus dividing the occupied silicon area by about 16.

Breakdown of the isolated snapback MOS transistors is difficult toachieve due to the presence of a second, parasitic bipolar transistor inwhich the collector is formed by the drain of the MOS transistor, theemitter by the source and the base by the body or bulk. This second,parasitic transistor is capable of stealing most of the current sent bya breakdown terminal to the drain of the MOS transistor. As a result,the post-breakdown resistance can vary between 100 ohms and 1 ohms,compared to the resistance of 10 ohms that is obtained in a reproduciblemanner when the non-isolated MOS structure is broken down.

The term isolated MOS transistor is understood here to mean a MOStransistor whose substrate and body are separated by a dielectric layer.Vertical and especially lateral isolation stresses encourage the use oflarge silicon areas to increase the dimensions of the body and decreasethe gain of the second, parasitic bipolar transistor.

Without excluding isolated MOS transistors, it is preferred to usenon-isolated MOS transistors that prevent the flow of leakage currentsfrom the body to the substrate. The body and the substrate are at thesame potential. Further, it is particularly advantageous to arrange thebody connector as close as possible to the drain for reasons of currentline distribution during breakdown. The body layer, a p-type layer in ann-MOS transistor, may or may not be ring-shaped. In both cases, the bodyconnector, i.e., the lead-out to the connection levels, is arrangedcloser to the drain than to the source as illustrated in FIG. 4.

The present invention thus enables series-arranged resistances to beadjusted in a precise and reproducible manner with the aid of economicalMOS transistors occupying a reasonable silicon area.

1. An integrated circuit comprising: a first MOS transistor comprising agate and a source connected together, a drain, and a body connected to avoltage reference; a first resistor connected in parallel to the drainand source of said first MOS transistor; a second MOS transistorconnected in series with said first MOS transistor, said second MOStransistor comprising a gate and a source connected together, a drain,and a body connected to the voltage reference; and a second resistorconnected in parallel to the drain and source of said second MOStransistor.
 2. An integrated circuit according to claim 1, furthercomprising a third MOS transistor connected in series with said firstand second MOS transistors, said third MOS transistor comprising a gateand a source connected together, a drain, and a body connected to thevoltage reference.
 3. An integrated circuit according to claim 2,further comprising a third resistor connected in parallel to the drainand source of said third MOS transistor.
 4. An integrated circuitaccording to claim 1, further comprising a first terminal connected tothe source of said first MOS transistor, said first terminal beingaccessible after said first and second MOS transistors are encapsulated.5. An integrated circuit according to claim 4, further comprising: asecond terminal connected to the source of said second MOS transistor,said second terminal not being accessible after said first and secondMOS transistors are encapsulated; and a third terminal connected to thedrain of said second MOS transistor, said third terminal not beingaccessible after said first and second MOS transistors are encapsulated.6. An integrated circuit according to claim 1, wherein each MOStransistor occupies an area less than 500 μm².
 7. An integrated circuitaccording to claim 1, wherein each MOS transistor occupies an area lessthan 200 μm².
 8. An integrated circuit according to claim 1, wherein thevoltage reference is ground.
 9. An integrated circuit comprising: afirst MOS transistor comprising a gate and a source connected together,a drain, and a body connected to a voltage reference; a first resistorconnected in parallel to the drain and source of said first MOStransistor; a second MOS transistor connected in series with said firstMOS transistor, said second MOS transistor comprising a gate and asource connected together, a drain, and a body connected to the voltagereference; a second resistor connected in parallel to the drain andsource of said second MOS transistor; an encapsulating materialsurrounding said first and second MOS transistors, and said first andsecond resistors; and a first terminal connected to the source of saidfirst MOS transistor, the first terminal being accessible externallyfrom said encapsulating material.
 10. An integrated circuit according toclaim 9, further comprising a second terminal connected to the source ofsaid second MOS transistor, said second terminal not accessibleexternally from said encapsulating material.
 11. An integrated circuitaccording to claim 10, further comprising a third terminal connected tothe drain of said second MOS transistor, said third terminal notaccessible externally from said encapsulating material.
 12. Anintegrated circuit according to claim 9, further comprising a third MOStransistor connected in series with said first and second MOStransistors, said third MOS transistor comprising a gate and a sourceconnected together, a drain, and a body connected to the voltagereference.
 13. An integrated circuit according to claim 12, furthercomprising a third resistor connected in parallel to the drain andsource of said third MOS transistor.
 14. An integrated circuit accordingto claim 9, wherein each MOS transistor occupies an area less than 500μm².
 15. An integrated circuit according to claim 9, wherein each MOStransistor occupies an area less than 200 μm².
 16. An integrated circuitaccording to claim 9, wherein the voltage reference is ground.
 17. Amethod for adjusting an integrated circuit comprising a first MOStransistor comprising a gate and a source connected together, a drain,and a body connected to a voltage reference; a first resistor connectedin parallel to the drain and source of the first MOS transistor; asecond MOS transistor connected in series with the first MOS transistor,the second MOS transistor comprising a gate and a source connectedtogether, a drain, and a body connected to the voltage reference; and asecond resistor connected in parallel to the drain and source of thesecond MOS transistor, the method comprising: applying a first voltageto the body, gate and source of the first MOS transistor; and applying asecond voltage to the drain of the first MOS transistor causingbreakdown thereof.
 18. A method according to claim 17, wherein the firstvoltage is constant, and the second voltage is a ramp voltage.
 19. Amethod according to claim 18, wherein the first voltage is ground.
 20. Amethod according to claim 17, wherein the voltage reference is ground.21. A method according to claim 17, further comprising encapsulating theintegrated circuit after applying the first and second voltages.
 22. Amethod according to claim 21, wherein the integrated circuit furthercomprising a first terminal connected to the source of the first MOStransistor, with the first terminal being accessible after the first andsecond MOS transistors are encapsulated.
 23. A method according to claim22, wherein the integrated circuit further comprises a second terminalconnected to the source of the second MOS transistor, the secondterminal not being accessible after the first and second MOS transistorsare encapsulated; and a third terminal connected to the drain of thesecond MOS transistor, the third terminal not being accessible after thefirst and second MOS transistors are encapsulated.
 24. A methodaccording to claim 17, wherein the integrated circuit further comprisesa third MOS transistor connected in series with the first and second MOStransistors, the third MOS transistor comprising a gate and a sourceconnected together, a drain, and a body connected in parallel to thedrain and source of the third MOS transistor.
 25. A method according toclaim 17, wherein occupies an area less than 200 μm².